Power Consumption and Linearization Performance of a Bit- and Frequency-Scalable AM/AM AM/PM Pre-Distortion on FPGA

This paper presents a power consumption and linearity characterization of an AM/AM AM/PM digital pre-distortion (DPD) on a 28-nm Xilinx Zynq-7000 field-programmable gate array (FPGA). This DPD is clock frequency and bit scalable up to 250 MHz and 16 bits to allow the exploration of the DPD power consumption vs. linearization performance trade-off with RF amplifiers. The resulting DPD power consumption can be as low as 4.7 mW in the 6-bit/50-MHz DPD case, and up to 60 mW for the 16-bit/250-MHz DPD case. With a 20-MHz 5G downlink modulated signal, a 12-bit/200-MHz DPD provides similar linearization performance to a 16-bit/250-MHz DPD while consuming 33% less Power.