Low Power Enhanced Trivium Implementation Using Parallel-Pipeline Technique

The power depletion is major fundamental needs in number of applications such as Internet of Things. The data transfer is major critical undertakings in IoT where more power is absorbed while carrying out cryptography. Lightweight cryptography and many encoding algorithms have been presented under this for software and hardware executions. Trivium is synchronous stream cipher in Profile II of ECRYPT comes under hardware implementation. In Low Power applications, trivium is widely used. Applied a new technique called Parallel-Pipeline technique where the pipeline technique is added to existing parallelization technique to analyze the dynamic power usage of Trivium. The Parallel-pipeline method increases the throughput of the design which is efficient and also the power has been reduced considerably while comparing to the parallelization technique which is implemented in FPGA using Vivado design suite 2016.4. The Parallel-Pipeline technique is also used with Enhanced Trivium to analyze the Power and Resource consumption in FPGA.