Dynamic Power Reduction in Huffman Design using 130 nm Technology Library

The demand for data compression and decreased dissipated power is motivated by many features, like following a new model for portable design, reliability effects, and flexibility. The new model of portable devices such as smartphones and laptops is the integral portion driving the demand for combining data compression and low power consumption. The need for portable devices is growing each year and is forecasted to grow more. In addition, a gating clock is the most important way of lowering power dissipation in a synchronous system. It keeps more power by partitioning the primary clock and distributing the clock signal to the logic pass only when there is a requirement for those blocks to be worked on. This research aims to design encoder and decoder modules by suggesting a new method of clock gating to realize decreased power dissipation. It reduced the power consumption by 32.28%. The proposed technique was achieved by using ASIC design and FPGA technology. In order to execute Huffman modules architectures, 130 nm Silterra libraries with Synopsys power compiler were utilized to evaluate the performance of the design. Huffman design architectures were formed using Verilog HDL's language (Quartus II 11.1 Web Edition (32-Bit). In addition to that, simulation was achieved by using ModelSim-Altera 10.0c (Quartus II 11.1) Starter Edition.