A CPU-FPGA Heterogeneous Acceleration System for Scene Text Detection Network

Scene text detection network, such as Connectionist Text Proposal Network (CTPN), takes CNN-RNN hybrid neural network as the main body, which can effectively recognize the text arranged horizontally in the image. However, complex structures and intensive calculations lead to longer network inference time. FPGAs have been widely used in data centers to accelerate neural network inference due to their flexibility and low power consumption. In this brief, a CPU-FPGA based heterogeneous acceleration system and a subgraph segmentation scheme for CNN-RNN hybrid neural networks are proposed. Winograd algorithm is applied to accelerate CNN. In RNN accelerating, fixed-point quantization, loop tiling, and piecewise linear approximation of activation function are used to reduce hardware resource usage and achieve a high degree of parallelization. CTPN is tested in our system with Intel Xeon 4116 CPU and Arria10 GX1150 FPGA, and the throughput reaches 1223.53GOP/s.