A 97-mW Bitwise-Early-Terminating Multiuser Detector for IDMA Systems

This brief presents a low-power multiuser detector that can terminate its processing earlier than usual for interleave division multiple access (IDMA) systems. As a baseline detection algorithm, a recently proposed bitwise early termination (BET) is adopted. Despite algorithmically feasible, the BET has never been realized in circuitry yet, pending the demonstration of physical practicality. For the first time ever, we efficiently implement the BET in a 65-nm CMOS technology, and demonstrate that it is indeed effective in realizing a fast and low-power detector. In doing so, we organize an essential set of information bits to examine the feasibility of the BET, and define a systematic procedure of manipulating the set of bits. In addition, we build an efficient hardware architecture that enables the proposed manipulation procedure. Through an extensive comparison with the state-of-the-art detectors in the literature, we validate that the prototype implementation completes the detection at the earliest, and draws the lowest power. Specifically, the proposed 16-user detector takes 3.98 iterations per bit, and dissipates 97 mW to process one 8192-chip frame. In contrast, even the latest low-power counterpart iterates 6 times, and consumes 24% more power.