Optimizing Data-flow Processor Architecture for Efficient Implementation of DSP Algorithms

The FPGA prototype of the Hybrid Architecture of Recurrent Signal Processor has shown promising results on the isolated word recognition (IWR) problem. This task is a subset of DSP algorithms. In expanding trial on a wide range of DSP algorithms, work has begun to increase the versatility of architectural solutions. The proposed solutions aim to reduce memory costs for storing tagged input data and optimize a number of computational pipeline modules. The article covers the implementation results of the FFT and a series of FIR filter algorithms. Some redundant, highly specialized for the IWR tasks blocks were excluded in the course of this work. The proposed architectural solutions increase the scalability of the architecture and reuse the introduced blocks to optimize the solution of other DSP tasks.