An Analog-to-information Converter Using Non-Uniform Sampling Architecture and SAR ADC

An analog-information converter with a non-uniform sampling architecture SAR ADC based was developed using the CMOS 180 nm process, having a maximum reference frequency of 40 MHz. Mathematical modeling of the device and numerical modeling of the schematic solution were carried out, taking into account the extraction of parasitic elements from the topology. The simulation results showed that this design is capable of recovering an input signal in a frequency band up to 20 MHz from 500 samples, although the ADC used in the AIС has a signal bandwidth of up to 500 KHz. The presented design allows the device to be used in AIC or ADC mode.