Improving Reliability-driven Resynthesis with Better Initial Structure

This paper presents a synthesis algorithm for combinational logic circuits in a given technology basis aimed at reliability optimization. Input data for the algorithm is a circuit in AIG format and a standard cell library, the output is Verilog description of the synthesized circuit. Several metrics based on logical masking probabilities are discussed providing different levels of precision for the cost of different amount of technology information ranging from none to reliability-oriented characterization results. The proposed algorithm is based on the classical tree covering algorithm adapted to optimize reliability characteristics. Signal propagation paths through inverting and non-inverting outputs of each tree are considered separately to give the algorithm more options while keeping cost function computation fast and accurate. The algorithm was tested on circuits from ISCAS'85 benchmark converted to AIGs via the ABC tool. Synthesized circuits were then given as an input to the reliability-driven resynthesis algorithm in order to further improve their fault tolerance. The final results were compared to those of the same resynthesis algorithm given ABC’s covering as an input.