FPGA Implementation of High-Performance Montgomery Modular Multiplication with Adaptive Hold Logic

This paper provides an efficient Montgomery modular multiplication technique, such as high-performance Montgomery modular multiplier, which is the most important arithmetic functional unit. The throughput of this multiplier is critical to the overall performance of these digital multiplication systems, which is measured in bits per second. The suggested work in this study proposes a Montgomery modular multiplier architecture that incorporates a unique adaptive hold logic (AHL) circuit to achieve a high level of performance. Because by the variable latency, the multiplier can deliver increased throughput while also adjusting the AHL circuit to prevent performance decline caused by the aging aware effect. Therefore, this proposed multiplier was developed using Verilog HDL and Synthesized in a Xilinx FPGA, which reduced the number of clock cycles required for operand pre-computation and conversion of format. As a result, high throughput can be achieved by hiding the additional clock cycles required for operand pre-computation and conversion of format. According to the experimental findings, our suggested design with 32-bit multipliers may provide up to a significant performance boost when compared to current 32-bit Montgomery Multipliers in terms of speed and efficiency.