Reducing Computational Complexity in Digital Circuit Designing using Ancient Mathematics: A Review

In this computer era, it is very important to optimize and improve the efficiency of VLSI design circuits for area, speed and power dissipation. To increase speed and decrease power consumption, technologies must be improved, while new algorithms must be investigated. Vedic mathematical sutras have always had the ability to effectively design and execute multiplications as well as divisions in order to enhance VLSI design circuits. As a result, it is critical to develop new designs for vedic multipliers which are more efficient in terms of area, power, & speed. In this work, several implementations of Vedic mathematics in digital circuits have been explored in terms of architectural implementation while considerations such as area, power, and speed are analysed.