Self-Heating Effects (SHEs) in Gate-All-Around FETs with Horizontally Stacked Multiple Junctionless Nanowires

In the advanced high-speed ULSI (ultra-large-scale integration) chip design, the reliability issue comes into the picture due to self-heating from the unbalanced power supply on the electrode's terminal. In this paper, the electrothermal (ET) behavior is introduced into newly gate-all-around (GAA) field-effect transistors (FETs) along with horizontally junctionless nanowire channels have been investigated and discussed in detail. The lattice temperature and drain current variation on thermal contact resistance have been widely analyzed using a Sentaurus TCAD device simulator. The saturation drain current and peak lattice temperature have considerably improved in multi junctionless nanowire devices with low thermal contact resistance. Therefore, the self-heating effects can be reduced significantly using the low thermal contact resistance.