TEL Based Pre-Scaler Design

Various applications demand low power consuming circuit styles under unbalanced load conditions. This paper focus on the design of a pre-scaler circuit based on improved Dual Rail Pre Charge Logic (iDDPL) for the same. It is a Time Enclosed Logic (TEL) based technique which can be categorised as an improved version of DDPL Logic. The basic gates like BUFF/INV, NAND/AND, XOR/XNOR and basic flip flops have been designed using iDDPL and it demonstrates reduced transistor count. The design of divide by 7 pre-scaler, designed using D flip flops based on iDDPL demonstrates a reduced power consumption of 3.66 mW. The circuits are simulated using Cadence® Virtuoso with 180 nm technology library.