Design and analysis of XOR-XNOR Circuit based Modified Hybrid Full Adder

This Low-power logic circuit design is increasing rapidly due to portable battery operated in electronic device. To design a low power and high performances circuit is one of major issues in the soft computing microprocessors and embedded systems. ALL the electronic processor systems comperises of Arithmetic Logic Unit (ALU), data path and control unit circuit. The Adder circuit is a basic component of ALU and most of the arithmetic operations consume high power and slowdown the processor speed. In this article, projected and executed a low power and high speed XOR-XNOR logic based modified Hybrid Full Adder (HFA) circuit for arithmetic operation. The XOR-XNOR logic circuit modules are extracted by Radhakrishna model, Naseri & Timarchi model and Abhishek & Jyoti model. The XOR-XNOR cell based modified HFA provides full swing outputs, reduce the delay and improve the performance simultaneously. The performance of the three modified hybrid full adder circuits is analyzed and compared in term of driving capability, delay, power performance and noise margin.