Simulation and synthesis of UART through FPGA Zedboard for IoT applications

Communication between any two electronic devices requires set of rules. These set of rules are called protocols. They ensure that data communication is done without any corruption. UART- Universal Asynchronous Receiver Transmitter is a serial communication protocol. UART consists of two main modules; UART Transmitter and UART Receiver. The transmitter section of UART consists several blocks like an FSM, a pulse Generator, odd/even Parity Generator, and Shift Register. In the similar way UART receiver consists an Edge Detector, FSM, shift register, even/odd parity checker and a B aud Rate Generator. Since the baud rate generator of both transmitter and receiver is same, so the baud rate(baud clock) of transmitter and receiver is also same. The UART transmitter has a 11-bit data frame. First bit is 1 start bit (indicates start of transmission), followed by 8-bit data that carries the information, 1 parity bit that indicates the parity(I this project odd parity is considered) and 1 stop bit (end of transmission). The baud rate generated in the work is 4 Mbps with input system clock of 64MHz frequency. The design and verification of UART is done using the Verilog HDL(Hardware Description Language). Xilinx Vivado-2020.2 version tool is us to implement the simulation and synthesis of UART. The targ FPGA board used for synthesizing the UART is ZedBoard, may be used for IoT applications.