Leakage Power, Current and Delay Analysis of Stack ONOFIC Based CMOS Circuits

Sub-threshold leakage current is increasing in CMOS circuits due to threshold voltage scaling. In CMOS (complementary metal oxide semiconductor) circuits all power dissipation techniques, most significant one is leakage power dissipation because of scaling down silicon technology. The productive nature of the device is increased if the reduction in power consumption. Thereby innovation of CMOS turned out as most popular in low power usage gadgets. Decrement in the linear leakage power loss and quadratic dynamic power loss are because of voltage supply reduction. For the utilization of standing power weak inversion current is the prime candidate due to leakage. Designing a CMOS circuit without leakage current is a challenging task. Few effective schemes are there for reducing power dissipation of VLSI (Very-large-scale integration) CMOS circuits. Here a circuit named stack ONOFIC is presented for mitigating the leakage current, propagation delay and leakage power in CMOS logic circuits. Inverter based CMOS logic circuits are utilized for representing the effect of presented scheme in CMOS circuits. Comparison between one of the reduction techniques as LECTOR and presented scheme is provided for showing the comparable reduction in terms of delay and dissipation.