Investigation of Potential FEC Schemes for 800G-ZR Forward Error Correction

With a record 400Gbps 100-piece-FPGA implementation, we investigate performance of the potential FEC schemes for OIF-800GZR. By comparing the power dissipation and correction threshold at 10
⁻¹⁵
BER, we proposed the simplified OFEC for the 800G-ZR FEC.