A 1.0-V 12-Gb/s Two-FIR Tap DFE with Tap Weighting Adjustable Filters

This paper proposes 12-Gb/s two finite impulse response(FIR) decision feedback equalizer(DFE). The architecture of the proposed DFE is composed of two summers, four slicers, four D-flip flops, and eight FIR filters. To compensate for 16.4dB channel loss with less power consumption, two finite impulse response filters are adopted in the proposed DFE, so that it can reduce cascaded stages of DFE. The proposed DFE has 2.92-mW power consumption with 1.0-V supply voltage, and this work has been verified in 28-nm CMOS process.