Pseudo C-2C ladder-based data converter technique

A C-2C ladder-based DAC architecture is potentially very attractive because of its small area, high speed and low power consumption. However, the parasitic capacitances on the interconnecting nodes of a C-2C ladder significantly deteriorate the linearity of the DAC and restrict its application. In this paper, a pseudo C-2C ladder structure is proposed. It maintains the advantages of conventional C-2C ladders and effectively compensates for the parasitic effects by adjusting the capacitor ratio a in a C-2/spl alpha/C ladder. As a result, high linearity may be achieved in standard CMOS technologies. The technique is illustrated with the design of a 12-bit CMOS DAC.