Design and Performance Analysis of ZYNQ Based Incremental PID-PWM Controller

With the rapid development of digital control techniques, there have been a great rise for using digital processors due to their adaptability, reduced cost, size and reliability. This paper presents a designed IP core of an incremental PID (Proportion, Integration, Differentiation) and PWM (Pulse Power Modulation) on Xilinx Zynq7035, aiming at simplifying the close-loop control of motor position, which driven by pulse powers. Firstly, PWM block is designed in Vivado2017 with Verilog Hardware Description Language (VHDL). Secondly, an incremental PID is built in Vivado High Level Synthesis (HLS) in C++, after C simulation, C synthesis and Co-simulation, it is packaged as intellectual property (IP) core for further applications. Thirdly, to demonstrate the effectiveness of our strategy, testbench is designed in HLS for the PID IP core, simulations are designed for both the PWM IP and the combined two IPs. All the results have shown our designed IP core is not only simple but precise in the close-loop position control of motor driven by pulse power. Moreover, usage of HLS leads to lower development time and rational allocation of hardware resources, which can be a powerful tool for realization of more complicated algorithms.