Circuit Design of a Frequency Synthesizer Device for High-Speed Data Transmission Systems

The paper analyzes the circuitry solutions and obtains the results of modeling a frequency synthesizer circuit based on a phase-locked loop (PLL), which contains the following components: phase detectors (PD), voltage-controlled oscillators (VCO), and a counter-frequency divider (C -FD). The main components of the PLL: PD, VCO and C-FD are implemented according to the classic CMOS-circuitry. The proposed solutions for the implementation of components based on CMOS-transistors with design standards of 65 nm made it possible to create a model of a frequency synthesizer required for the implementation of onboard devices using OFDM technology.