A Geometrical Optimization Rule of the Synaptic Pass-Transistor for a Low Power Analog Accelerator

We present a simulation framework on a geometrical optimization rule of the synaptic pass-transistor (SPT) for a low power analog accelerator (AA). Here, the SPT is a synaptic transistor (Syn-Tr) in series with a load resistor to be scaled with respect to a geometrical ratio between a channel length and width of the Syn-Tr. When only the load resistance is increased for the reduction of the power consumption of the SPT, a synaptic characteristics (e.g. a synaptic dynamic ratio, DR
_w
) is hard to be maintained. To overcome this, the channel geometrical ratio and scaling factor of the load resistance are required to be increased equally, thus a geometrical optimization rule. Here, the load resistance is equivalent to a geometric mean where two extreme cases of the synaptic full facilitation and full depression are considered. To verify the proposed rule, we perform a semiconductor device simulation for a static and pulsed characteristics of the SPT. When the SPT is scaled based on the geometrical optimization rule, from the simulation results, it is found that the static-power consumption is decreased while maintaining the DR
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. As a trade-off relation, however, the noise power-spectral-density is found to be increased due to a higher thermal noise associated with a higher total resistance of the scaled SPT. Here, the increased noise power-spectral-density of a single SPT may affect the performance of the AA based on the SPT-array, so we also show a crossbar simulation, checking the classification accuracy against a standard dataset (e.g. MNIST).