Design of ternary flip-flop cells using Maximum/Minimum logic operators in carbon nanotube technology

The usage of ternary logic in the digital design leads to the reduction in interconnect complexity and chip area which helps to improve circuit performance in various applications. This work presents the digital logic realization of ternary flip flop structures using ternary Min./Max. operators. The circuit implementation is based on carbon nanotube field effect transistors having the exceptional electrical characteristic of threshold voltage variations by employing CNTs with different diameters. The three-valued logic benefit of enhanced processing capability is employed in designing sequential logic modules. To optimize the performance efficiency of flip-flop designs, the ternary logic family with transistors of suitable on-state driving capability are employed in the realization of NAND/NOR logic cells. Further to analyze the performance of the proposed three valued flip-flops, experimental results are computed considering the 32nm CNTFET Stanford model taking Synopsis HSpice tool. Based on the simulation results, it is shown that presented ternary flip-flop designs provide significant saving (upto 50%) in terms of energy consumption(PDP) as compared to recent counterpart.