Performance Analysis of Arithmetic Unit for IoT Applications

At present the ultimate aim in digital system designs, especially at the gate level and lower levels of design abstraction, is power optimization. Adders are nearly a universal component of today’s integrated circuits. Most of the research is based on the design of high-speed adders to execute addition based on various adder structures. This paper discusses the ideal path for selecting an arithmetic unit for IoT applications. Based on the analysis of eight types of 16-bit adders, Carry Look-ahead (CLA) adder was found to produce low power. Additionally, Multiplier and Accumulator (MAC) unit is implemented with Booth multiplier by using the low power adders in the order of preference. The design is synthesized and verified using Synopsys Design Compiler and VCS. Then it is implemented by using Cadence Encounter. The total power consumed by the CLA based booth multiplier is 0.03527mW, the total area occupied is 11260 um2 and the speed is 2034ps.