Efficient Hardware Implementation of Error Correcting Codes Classification Algorithm

In this paper, we present efficient hardware structure of Gauss-Jordan Elimination Through Pivoting (GJETP) based error correcting code classification algorithm, in order to provide real-time solution for code recognition in non-cooperative context. We originality proposed to modify the architecture of traditional GJETP by using two type of processing units in the paper. Compared to normally used hardware architecture, the proposed hardware architecture based elimination algorithm significantly unleashes the working frequency and tightens the power consumption to a great deal. Further results illustrates that there are obvious acceleration using the proposed approach than software based method with the acceleration rate over 100 times.