Clock Domain Crossing Verification Challenges

Clock Domain crossing is one of the critical aspects of chip design. As the technology node shrink, more IPs can be squeezed into single chip, the chip architecture complexity also increases with more features included. Hence, clock domains crossing probability also increase as more clocks domains co-exists within single chip. The need of clock domain crossing verification also increases and no longer enough to be simple design review and verification. The intend of this paper is to provide an overview of clock domain crossing verification challenges and watchouts. Hopefully it will benefit the community.