Energy-Efficient In-Memory Binary Neural Network Accelerator Design Based on 8T2C SRAM Cell

We present an in-memory binary neural network (BNN) accelerator based on 8-transistor and 2-capacitor (8T2C) SRAM cell. The proposed SRAM computing-in-memory (CIM) cells rely on DRAM-like charge sharing operations to avoid undesirable static currents and potential read-disturb problems in conventional resistive SRAM-CIM designs. In addition, unlike the previous capacitive SRAM-based CIM designs, the proposed SRAM CIM does not consume energy when the input value is 0, thereby achieving the higher energy efficiency in benchmark testing. Measurement results of the 256
$\times $
64 array prototype chip in the 28-nm CMOS technology showed 3182 TOPS/W at 0.7 V which is
$4.7\times $
higher energy efficiency than that of a state-of-the-art design.