Design and Optimization of a Pruning-Efficient DCNN Inference Accelerator

This paper presents the pruning-efficient architecture of DCNN inference accelerators. The sparse representation with the row-bank structure can compress and decompress the pruned DCNNs with little hardware overhead. The hardware-aware pruning flow is also proposed for our architecture. The experiment results show that our pruned model can be accelerated 1.2× to 2× faster than others with higher accuracy at the same sparsity levels. Besides, our pruning-efficient accelerator is more effective than the row-stationary accelerator. With a slight accuracy drop, the proposed accelerator can perform ResNet-50 2.7× to 4.5× faster while reducing the energy-delay-product (EDP) by 71% to 88%. Therefore, DCNN acceleration can be achieved with the co-optimization of both accelerator design and structure pruning for the trade-off among model accuracy, latency, and energy consumption.