A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement

This article proposes a mismatch self-compensation latch-based true random number generator (TRNG) that harvests a metastable region’s enhanced random noise. The proposed TRNG exhibits high randomness across a wide voltage (0.3–1.0 V) and temperature (−20 °C–100 °C) range by employing XOR of only four entropy sources (ESs). To achieve a full entropy output, an 8-bit von Neumann post-processing with waiting (VN8W) is used. The randomness of the TRNG’s output is verified by NIST SP 800–22 and NIST SP 800-90B tests. The proposed TRNG, fabricated in 130-nm CMOS, achieves state-of-the-art energy of 0.186 pJ/bit at 0.3 V with a core (four ESs + XOR circuits) area of 661
$\mu \text{m}^{2}$
and a total area of 5561
$\mu \text{m}^{2}$
, including VN8W. The robustness against power noise injection attacks is also demonstrated. An accelerating aging test revealed that the TRNG achieves a stable operation after 19 h of aging, which is equivalent to the 11-year life reliability. The mismatch-to-noise ratio analysis revealed that the XOR-OUT of TRNG core has more than 6
$\sigma $
robustness against random mismatch variations.