An architecture of small-scaled neuro-hardware using probabilistically-calculated pulse neurons

Proposes an architecture of a neuro-hardware that can be realized on a far smaller-scaled circuit compared to the conventional approach. In order to reduce the scale of the circuits, the architecture employs a method of computing the membrane potential and the sigmoidal function by encapsulating the probability properties into the relative delay between two pulses of different signal lines. The proposed architecture enables us to integrate more than one hundred of neurons on a latest FPGA chip, which means thirteen-fold miniaturization compared to conventional architecture.