A 1-58.125Gb/s, 5-33dB IL Multi-Protocol Ethernet-Compliant Analog PAM-4 Receiver with 16 DFE Taps in 10nm

Demand for higher aggregate data rates in digital computing and storage services requires higher per-lane throughput, better reliability, and improved power- and area-efficiency. Support for a range of data transmission protocols in a single IP reduces risk, cost, and time to market. Beyond 56Gb/s, most SerDes IPs have adopted ADC-based architectures. While ADC-based receivers can offer higher link margin and higher data-rates at the cost of power and area, the difficulty of implementing higher DFE taps poses a challenge for reflective and noisy channels. On the other hand, analog designs must meet the tap1 timing constraint and require accurate slicers operating across process and temperature variation. Specific design techniques are required to overcome these challenges. Previously reported speculative decision schemes are not efficient in PAM-4 due to the large number of slicers and multiplexers required. This paper presents the receiver of an analog multi-protocol SerDes transceiver at data rates of 2-58Gb/s PAM-4 and 1-32Gb/s NRZ with 16 data and 3 edge DFE taps. This transceiver fully supports both Ethernet/OIF and PCI-Express Gen1-4 as well as full or partial support of CPRI, JESD, USB, SATA, GPON, HDMI, DisplayPort, OTN, SDI, and SONET. Circuit techniques applied include background slicer threshold optimization using dynamic swapping, DFE taps with cross-coupled MOS capacitors and cascode devices for load isolation, edge taps and sampling point optimization. This receiver achieves pre-FEC BER<10
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over dynamic temperature variation of -20C to 105C in a 10nm process technology and channel insertion loss of 5-33dB compliant with the Ethernet standard. Receiver area is 0.14mm2 and power at 58.125Gb/s is 259mW from 1V and 1.8V supplies.