A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving −79dBc Reference Spur and 0.496mW/GHz Power Efficiency

The digital injection-locked clock multiplier (ILCM) using ring oscillators (ROs) is a superior choice for clock generation due to its ease of scaling, compact area, and prominent jitter performance. However, the periodic phase realignment in an ILCM can cause a deterministic phase error in the injection moment, which generates an extremely poor reference spur (e.g., −50dBc). Several digital calibration techniques [1]–[5] have been introduced to reduce the reference spur. The key is to first detect sources of non-idealities (e.g., imperfect injection timing, frequency drift, and slope modulation), and then to enable a specific calibrator to correct each error source. Unfortunately, there are many non-idealities that can affect the injection performance, such as supply ripples, charge injection of the switches, and clock feedthrough, making it impractical to employ multiple calibration loops to simultaneously mitigate each of them. On the other hand, conventional phase-error-detection schemes [2]–[3], [5] suffer from the timing race between the calibration loop and the injection, and hence elaborate timing control is required to extract errors. This timing-control logic is sensitive to process, voltage, and temperature (PVT) variations, leading to inadequate mitigation of the reference spurious power.