Implementation of Decision Tree Classifier on FPGA

This paper proposed the implementation of decision tree classifier on FPGA. A comma separated value format is accepted by the framework and then it does many steps to form a trained model. Subsequently the framework forms two formats of decision tree based classifier viz Joint Photographic Experts Group and Verilog/VHDL. The hierarchy of generated tree is represented by JPEG (image) representation and VHDL /Verilog code is used as a the representation of trained model hardware description. The current framework uses the Verilog/VHDL in FPGA DESIGN VALIDATION FLOW. The novelty framework bridges the gap between M.L. model training and its hardware designing.