Fast Search and Efficient Placement Algorithm for Reconfigurable Tasks on Modern Heterogeneous FPGAs

To date, only a tiny fraction of reconfigurable task placement algorithms is targeted at modern heterogeneous field-programmable gate array (FPGA) architecture, and they often focus on determining the final placement location and pursuing placement quality. Hence, their real-time performance is poor because feasible location searching and placement speed are rarely taken into consideration. In this article, we propose a fast search strategy based on characteristic target gene sequence (CTGS) and an efficient placement algorithm called prioritization-based minimum cost and marginal compact (P2MC). CTGS ascertains tasks’ feasible locations quickly by regarding the relatively few heterogeneous resources on FPGAs as search targets. P2MC first introduces prioritization heuristics based on task characteristics (PHTC) to presort tasks in order to improve the placement success rate and then select the final location according to the principle of minimum cost and marginal compact (2MC) so as to reduce the fragmentation of free space. The proposed algorithms are verified and evaluated on Xilinx’s mainstream FPGA families Virtex-5/6/7. Results show that CTGS can accelerate the search speed of tasks’ feasible locations by about four to five times, and P2MC can further balance placement speed and success rate. Compared with state-of-the-art heterogeneous task placement algorithms, P2MC can either increase both placement speed and success rate (by about 29% and 4.5%, respectively) or significantly increase the placement speed (by 20 times) at the expense of a bit of placement success rate (by only 5.8%).