Design and Implementation of Array Multiplier using Compressor for Low Power

Multiplication is an imperative part of Image Processing, and Digital Signal Processing (DSP) applications. The high speed is required in processing that is achieved by using Parallel Array Multiplier. In this paper, a conventional Array Multiplier is compared with conventional m:2 and m:3 compressor. The comparison of device utilization summary, memory used, delay and power for conventional array multiplier and compressor design is also presented in the paper. A new hybrid 16x16 bits multiplier that use both compressor module m:2 and m:3 has been proposed to achieve the benefits of both. The synthesizable structural VERILOG code is used to simulate and implement different architectures of multiplier.