Implementation and Performance Analysis of 2:1 Multiplexer using Different Logic Families at 130nm Technology

Multiplexer (MUX) which is also familiar as an input or information selector and a device that opts joining different analog or digital signal inputs and ahead the marked put in to sole yield. It is first of the salient components which upgrade the effectiveness of data transversal. Multiplexers are used to expand the amount of the data that can transferred over a line of network with given bandwidth over a time of period. There are different multiplexers for digital and analog signals. A digital multiplexer has digital input signals coming from different data-acquisition networks. In this project, a 2:1 multiplexer is analyzed by numerous CMOS logics which are Pseudo NMOS logic, Static CMOS logic, Dual-Rail Domino logic and Domino logic which recognize the foremost families that is appropriate for the outline of greatest methods of multiplexer. The execution is implemented in VLSI automation because it have characteristics such as less size, less cost, great operating speed and less power. The accomplishment research of the multiplexer using different logic families are executed in DSCH, Micro wind and Mentor graphics at 130nm.The results gathered shows that the Domino logic method based 2:1 multiplexer is the well-organized method. The Domino logic outshines the different logics that the work recommends that the giant elevated different level multiplexer with shallow power and power delay product can be accomplished using method of Domino logic.