Research on Vector Structure of Neural Network Algorithm Based on RISC-V

To solve the problem of low computational efficiency and energy efficiency in the general-purpose processor neural network, and low flexibility of the dedicated processor, a scalar plus vector processor is designed based on the RISC-V instruction set Structure. Through software and hardware co-design, a dedicated access instruction design is adopted for the algorithm structure of the neural network, and vector instructions are used to accelerate operations such as activation, pooling, and convolution. The extended instructions of the RISC-V processor are decoded in the processor decoding stage, and then the vector unit is called at the execution stage to accelerate the neural network. Experimental results show that the computing performance of the processor at 200MHz reaches 60.18 GOP/s, which is an increase of 417.91% compared to the processor, and the energy consumption ratio reaches the mainstream level of similar designs.