5-nm Low-Power SRAM Featuring Dual-Rail Architecture With Voltage-Tracking Assist Circuit for 5G Mobile Application

Voltage auto tracking cell power lowering (VACPL) write assist circuit and voltage auto tracking assist (VATA) are proposed for low-power SRAM with dual-rail architecture to mitigate the SRAM design margin issues. VACPL controls the cell voltage adaptively with respect to the dual-rail offset voltage to maximize bitcell write-ability. The access disturb is recovered by lowering the WL voltage level with VATA at the large dual-rail offset voltage condition. A 5-nm EUV FinFET test chip demonstrates 210-mV
$\text{V}_{\mathrm{ MIN}}$
improvement and
$4.7\times $
larger range of operating voltage with VACPL. The proposed VACPL and VATA achieve 95.2% leakage power reduction by lowering VDDC by 400 mV in 5-nm 5G mobile device.