Extended Scale Length Theory Targeting Low-Dimensional FETs for Carbon Nanotube FET Digital Logic Design-Technology Co-optimization

We present a new extended scale length theory targeting low-dimensional FETs and derive a new Carbon Nanotube FET (CNFET) leakage compact model which also includes inelastic band-to-band tunneling. We accurately predict CNFET minimum drain leakage (spanning 10¹⁰ range) within 3x vs. experimentally calibrated Non-Equilibrium Green Function (NEGF) simulations (10^5x error without our model). Our extensive design-technology co-optimization (DTCO) quantifies, for the first time, large Energy Delay Product (EDP) benefits (up to 4.8x - 7x depending on the reference) of CNFET ring oscillators (vs. silicon NanoSheet, silicon ForkSheet, silicon CFET) at the 2nm node.