Dielectric Confinement Impact on Electrical Performance of Highly Scaled Saddle-Fin Cell Transistor for High Density DRAM

Dielectric confinement (DC) effect is a phenomenon in which as the diameter of the silicon nanowire (SNW) decreases, the efficiency of dopant activation in silicon is reduced due to the dielectric surrounding the SNW. Inevitably, saddle-fin cell transistor for high density DRAM has silicon pillars like SNWs which are connected to storage capacitance and bit-line through polysilicon or silicon. In this paper, we implemented a dielectric confinement model in TCAD and fabricated saddle-fin cell arrays and specific test element groups for extracting resistance components using 20 nm technology node. It is found that the DC effect does not significantly affect the resistance values of storage node contact (SNC) and bit-line node contact (BLC) up to 20nm node, but becomes significant beyond sub 20nm node. The DC effect increases the variance of external resistance as well as the resistance value. This result indicates that it is necessary to find a proper solution to mitigate the DC effect, especially when using low-k materials to reduce the parasitic capacitance for sensing margin beyond sub 20nm technology node.