Si MOS and Si/SiGe quantum well spin qubit platforms for scalable quantum computing

We discuss the engineering and physics of both Si MOS and Si/SiGe quantum well based spin qubit devices fabricated in a process compatible with CMOS high volume manufacturing. This includes new process innovations around buffer engineering, EUV lithography for gate pitch scaling, and the creation of a fully electrostatically defined planar quantum dot flow not requiring STI for confinement. Charge sensing, tunnel coupling, and valley splitting are characterized down to the single electron limit for both systems. The gate dielectric interface quality is correlated to potential landscape control and spurious dot formation. While coherent control of spin is demonstrated in both systems with comparable gate fidelity (>99.1%) and coherence times (> 1ms), the scaling challenges are very different, with Si MOS requiring dielectric interface Dit improvements for spurious dot reduction and the Si/SiGe system requiring improvements to valley splitting.