System Design Technology Co-Optimization for 3D Integration at <5nm nodes

Partition of monolithic 2D (M2D) chip and heterogeneous integration of resultant chiplets are inevitable in the near future due to rising cost of transistor and complexity of process. 3D stacking is required to maintain tight cross-IP communication and fit into the limited footprint over Printed Circuit Board (PCB). We discuss criteria of choice for the 3DIC technology flavor and logic chiplet scaling knobs in terms of optimized key performance indicators (KPI) at system level.