A 20Mb Embedded STT-MRAM Array Achieving 72% Write Energy Reduction with Self-termination Write Schemes in 16nm FinFET Logic Process

We present the low energy write techniques and measurement results of a 20Mb embedded STT-MRAM test chip in 16nm FinFET logic process. Self-termination write schemes with slope write voltage and current pulse and variable parallel bit write sequence are proposed to reduce total write energy consumption by terminating write pulse adaptively according to the characteristics of each STT-MRAM cell and achieves 72% write energy reduction and 50% total write pulse time reduction.