High-Density and High-Speed 4T FinFET SRAM for Cryogenic Computing

Cryogenic on-chip memory requires low energy consumption for enabling cryogenic and exascale computing. With FinFET Si data calibration, this work clearly demonstrates that the 4T cryogenic SRAM surpasses various kinds of the 6T SRAM in area, speed, stability, and energy efficiency at both 77K and 300K. Compared to the 6T SRAM with regular threshold voltage in high-density design (6T-RVt-HD) at 300K, the 4T cryogenic SRAM at 77K shows 20.3% cell area reduction, 44% reduction in read access time, 46% improvement in write time, 2.3× improvement in write stability, and 53% reduction in energy-delay product (EDP). Considering the cooling energy consumption at 77K, the 4T cryogenic SRAMs exhibit 33% EDP reduction compared to the 6T-RVt-HD SRAMs at 77K. The proposed high-density and high-speed 4T cryogenic SRAMs with low access energy and superior stability could be promising candidates for cryogenic high-performance-computing (HPC) applications.