pHEMT Behavioral Model with Gate- Lag Effects Applied to The Dynamic Simulation of Switching Speed

When pHEMT devices are integrated with GaAs HBTs, design functionality and flexibility in the RF front-end module greatly increases. However, the occasional occurrence of slow switching pHEMT devices can result in power vs. time (PVT) failures at the module level. This paper presents a behavioral model that includes gate-lag / charge trapping effects. It can be used in dynamic simulations to estimate switching speed in circuits so that potential timing problems can be identified early in the design cycle. The model can be used to set pass/fail limits for screening tests, identify design improvements, and/or optimize performance.