An Optimal Design and Implementation Method of High Speed Digital Down Conversion Based on FPGA

In the electronic warfare, AD sampling rate and instantaneous bandwidth are increasing. The traditional DDC cannot meet the high sampling rate application. In order to solve this problem, an optimization design method based on the parallel digital down conversion and polyphase filtering is proposed. Firstly, the mathematical model of high-speed digital down-conversion is deduced and its implementation architecture is designed efficiently based on the traditional DDC, the high-speed down conversion structure of parallel frequency conversion and filtering is designed. Secondly, the parameters such as the frequency phase of parallel frequency conversion and the calculation method of multi-path filter coefficients are given. The hardware implementation shows that the optimized design method is correct and easy to implement, it can meet the application requirements of digital down conversion under the high sampling rate of electronic warfare.