Synchronous and Asynchronous Implementation of Radix-2 Booth Multiplication Algorithm

Multiplication is one of the most common operations used in any program. Program working on massively large data always requires high computation power. In the age of big data, conventional general-purpose CPU based on Von Neumann architecture is no longer enough to satisfy high computation demand. Field Programmable Gate Array (FPGA) can perform hardware acceleration of any program. Since multiplier is the slowest component in any hardware accelerator, thus faster and re-configurable multiplier which can handle integers of any size must be implemented on FPGA. In this paper, we implemented both synchronous and asynchronous radix-2 booth multiplier using Verilog HDL on a Xilinx FPGA. We found that simulation time of asynchronous radix-2 booth multiplier is faster than synchronous radix-2 booth multiplier but synchronous radix-2 booth multiplier consumes fewer resources than asynchronous radix-2 booth multiplier.