Compact PUF Design With Systematic Biases Mitigation on Xilinx FPGAs

Physical unclonable functions (PUFs) are a strong and secure root source for identification and authentication applications. PUFs are especially valuable in FPGA-based systems because FPGA designs are vulnerable to intellectual property (IP) thefts and cloning, which PUFs protect against by generating random but device-specific bitstrings. Theoretically, the randomness of PUFs originates from variations in the manufacturing process. PUFs should be free of deterministic variation owing to the systematic bias among all chips of the same model. Correspondingly, one of the major challenges for FPGA-based PUFs is the difficulty of avoiding systematic bias between nominally matched delays in competing paths. In this paper, a deep investigation into the LUT structure on a Xilinx FPGA was conducted. Based on the investigation findings, a compact PUF design based on programmable look-up table paths is proposed. The proposed intertwined structure and the novel 2-phase, 2-pass scheme significantly reduced the impact of systematic biases in the Xilinx FPGA LUT. The proposed PUFs exploit random variations in LUTs, thus exhibiting very good uniformity and uniqueness among the generated bitstrings.