Fault-tolerant Design of Power Edge Computing Processor Based on Full-hardware Dual-core Lockstep

With the continuous reduction of integrated circuit process nodes and the increasingly complex working environment of power edge computing chips, the reliability of processors is facing severe challenges. The current fault-tolerant methods of commonly used processors either occupy a large area, or have high performance overhead and insufficient real-time performance. In response to this problem, this paper proposes a full-hardware dual-core lock-step power edge computing processor fault-tolerant design method and specific implementation, then builds a simulation-based fault injection platform, and finally conducts a lot of tests on its related indicators. The test results prove that the fault-tolerant design has excellent reliability and real-time performance, while reducing the area cost, and is particularly suitable for low-cost, real-time requirements.