A 5–11 GHz 8-bit Precision Passive True-Time Delay in 65-nm CMOS Technology

In this paper, we present an 8-bit precision passive true-time delay (TTD) operating at 5–11 GHz in 65-nm CMOS technology. To achieve a precision time delay control, the 8-bit TTD employs a 4-bit time delay circuitry that utilizes two
LC
delay networks in parallel to reduce the effects of the nonideal lumped components and layout imbalance of a conventional TTD. To design an 8-bit TTD, a 4-bit TTD with conventional
LC
networks was also used for the 5
^th
bit to the 8
^th
bit (MSB) time-delay for coarse delay control. The implemented 8-bit TTD circuit achieved a minimum delay of 1.56 ps and a maximum delay of 400 ps, demonstrating the smallest loss per delay among the recently reported state-of-the-art silicon-based TTDs without dissipating any DC power and with a chip area of
$2.76\times 1.01$
mm
²
.