Design of an Energy efficiency Comparator using Dynamic Cancellation

There has been an increasing number of people using portable devices due to their low power and for handheld. Symmetric circuits represent the highest performance stability and design efficiency. Dynamic comparators are commonly utilized in the design of high-speed Analog-to-digital Converters and are quite simple to implement. The conventional comparator uses two-phase clocking and maximum drive current. To overcome the disadvantages. A novel comparator with low power and low delay has been proposed. At 1.8 voltage supply, the proposed comparator was designed and implemented in Cadence gpdk 180nm Technology. Layout results in 180nm CMOS technology indicate a 75 percent reduction in power consumption and a 25 percent reduction in delay time.